1. Technical Field
The present invention relates to FPGAs (Field-Programmable Gate Arrays), and more particularly, to testing of FPGAs embedded in an ASIC (Application-Specific Integrated Circuit).
2. Related Art
An FPGA (Field-Programmable Gate Array) and an ASIC (Application-Specific Integrated Circuit) can be combined to form a hybrid IC (integrated circuit) so that the hybrid IC can have the advantages of both the FPGA (design flexibility) and the ASIC (low power, high performance, and low test pin count).
Testing a standalone FPGA typically consists of exhaustively testing the logic blocks and interconnect resources of the FPGA through a series of structural tests. These structural tests configure the standalone FPGA in different ways and require access to all input/output (I/O) pins of the standalone FPGA. Similarly, testing the FPGA in the hybrid IC consists of essentially the same structural tests. The problem is how to access all I/O pins of the FPGA in the hybrid IC given the low test pin count of the hybrid IC.
Therefore, there is a need for a novel structure and testing method for a low test pin count, hybrid IC comprising an ASIC and multiple FPGAs.